Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
With the proliferation of networking and computing technologies, demand for further scaling down of memory devices has resulted in smaller and denser memory devices. However, further attempts may be hampered by core memory functionality being based on storage of one bit (a “0” and a “1”) in each memory cell. To increase memory density, attempts are made to store more than one bit on one device, such as mirror-bit approach. In conventional flash memory devices, one channel may be used to detect the current and threshold voltage shift caused by the charges stored in the gate.
Conventional attempts to increase memory density may use improvements and/or alternative or additional solutions in order to effectively provide higher capacity memory devices without increasing a size of the device.